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Embedded Vernier TDC with sub-nano second resolution using fractional-N PLL

Journal article
Authors Lars Bengtsson
Published in Measurement
Volume 108
Pages 48-54
ISSN 0263-2241
Publication year 2017
Published at Department of Physics (GU)
Pages 48-54
Language en
Keywords Time-to-digital converter; Phase-locked loop; Vernier; FPGA; Fractional-N PLL
Subject categories Signal Processing, Embedded Systems, Electronics, Accelerator Physics and Instrumentation


A novel implementation technique for Vernier-based time-to-digital converters is reported. It is based on fractional-N phase-locked loops which allows the design of Vernier clocks with very close frequencies. The Vernier registers comparing counter values have been implemented in hardware in order to guarantee minimum detection latency of the moment of coincidence. Two Vernier clocks with close frequencies increment two 24-bit counters in a Cyclone V FPGA. A Vernier TDC with a demonstrated time resolution of 476 ps is reported. It is also established that the time resolution limit that can be achieved with the suggested design is 10 ps.

Page Manager: Webmaster|Last update: 9/11/2012

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